This content provides a system-level understanding of power and thermal issues related to designing with the Versal™ ACAP.

In this content you will learn about Versal™ ACAP architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal ACAPDescribing the different engines available in the Ve...

This content introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is u...

This content introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications ...

This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and A...

This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...

This content provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool.

This course helps you to learn about Versal™ ACAP architecture and design methodology. The emphasis of this course is on:▪ Reviewing the architecture of the Versal ACAP▪ Describing the different engines available in t...

This course helps you to learn about Versal™ ACAP architecture and design methodology. The emphasis of this course is on:▪ Reviewing the architecture of the Versal ACAP▪ Describing the different engines available in t...

This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is us...