Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications.The emphasis of this course is o...
This content is structured to provide designers with an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family. Special emphasis is placed on the Data Converter and Soft-Decision FEC blocks.Po...
This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and A...
This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...
Learn how to build and run complex multimedia applications targeting Zynq® UltraScale+™ MPSoC EV devices with the help of the GStreamer framework. This course also illustrates how the use of the hardened video codec u...
This content provides embedded systems developers experience with creating an embedded Linux system targeting Xilinx SoCs using the PetaLinux tools.Updated 2.2022 - v2021.2
This content introduces the concepts, tools, and techniques required for software design and development for the Zynq® System on a Chip (SoC), Zynq UltraScale+™ MPSoC, using the Vitis IDE.The focus is on:Reviewing the...
This workshop demonstrates the tools and techniques required for software design and development using the the Vitis™ unified software platform.The emphasis of this course is on:Reviewing the basics of using the Vitis...
This content provides software developers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a software development perspective.Updated 3.2022 - v2021.2
