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Virtual - Accelerating Applications with the Vitis Unified Software Environment
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Virtual - Advanced Hardware Debugging Techniques Using Vivado Design Suite (Hardent course)
This Xilinx training will show you how to use the debug tools in the Vivado® Design Suite to address advanced verification/debugging challenges. As FPGA designs become increasingly more complex, designers continue to ...

Virtual - Advanced Timing Closure Techniques for the Vivado Design Suite (Hardent version)
Achieving repeatable and reliable timing is the designer’s ultimate goal. The task of writing timing constraints and validating the design against those constraints is commonly referred to as Timing Closure. This pr...

Virtual - Advanced Universal Verification Methodology (UVM) (Hardent version)
In this Advanced UVM class, you will gain experience in dealing with these and other test bench challenges. The class works through various test bench issues and challenges providing solutions. You will be able to app...

Virtual - Advanced Verification with OSVVM (PLC2 version)
Today’s FPGA and ASIC designs have drastically increased in size and complexity since the very beginning of digital hardware design. These elaborate circuits are described as a hierarchy of sub-systems in hardware des...

Virtual - Advanced VHDL
Increase VHDL proficiency by learning advanced techniques for writing more robust and reusable code.The focus is on:Writing efficient and reusable RTL, testbenches, and packagesCreating self-testing testbenchesCreatin...

Virtual - Arm Cortex-A53/R5 for Zynq UltraScale+MPSoC (Doulos version)
This course covers the software aspects ofdesigning with an Arm® Cortex®-A53 MPCore based device, highlighting the core architecture details and the Xilinx® Zynq® UltraScale+™ implementation choices.Topics include the...

Virtual - C-based design: High-Level Synthesis with the Vivado HLx Tool
Provides a thorough introduction to the Vivado High-Level Synthesis (HLS) tool.The focus is on:Covering synthesis strategies and featuresImproving throughput, area, interface creation, latency, testbench coding, and c...

Virtual - Class Based SystemVerilog Verification (Doulos version)
SystemVerilog (IEEE 1800™), the successor to the Verilog® hardware description language, has become the dominant language standard for functional verification. SystemVerilog significantly enhances the capabilities of ...

Virtual - Comprehensive SystemVerilog (Doulos version)
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