Xilinx-Prod-LMS Offerings


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Vivado Design Suite を使用した FPGA の設計 1
このコースでは、FPGA デザインの初心者向けのデザイン フローなど、Vivado® Design Suite の入門内容を提供します.

Virtual - Versal Live Online Workshop Compendium - 3 AI Engine (SO-Logic in German)
Illustrating the AI Engine architectureDesigning single AI Engine kernels using the Vitis™ unified software platformDesigning multiple AI kernels using data flow graphs with the Vitis IDEReviewing the data movement be...

Virtual - Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications. Also learn how to run designs o...

Virtual - Advanced VHDL
Increase VHDL proficiency by learning advanced techniques for writing more robust and reusable code.The focus is on:Writing efficient and reusable RTL, testbenches, and packagesCreating self-testing testbenchesCreatin...

Virtual - C-based design: High-Level Synthesis with the Vivado HLx Tool
Provides a thorough introduction to the Vivado High-Level Synthesis (HLS) tool.The focus is on:Covering synthesis strategies and featuresImproving throughput, area, interface creation, latency, testbench coding, and c...

Virtual - Debugging Techniques Using the Vivado Logic Analyzer
Debugging Techniques Using the Vivado Logic Analyzer

Virtual - Designing an Integrated PCI Express System
Learn how to implement a Xilinx PCI Express® core in custom applications to improve time to market with the PCIe® core design.The focus is on:Constructing a Xilinx PCI Express system within the customer education refe...

Virtual - Designing FPGAs Using the Vivado Design Suite 1
Offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.The course provides experience with:Creating a Vivado Design Suite project with sourc...

Virtual - Designing FPGAs Using the Vivado Design Suite 2
Learn how to build a more effective FPGA design:The focus is on:Using synchronous design techniquesUtilizing the Vivado® IP integrator to create a sub-systemEmploying proper HDL coding techniques to improve design per...

Virtual - Designing FPGAs Using the Vivado Design Suite 3
This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to d...