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Virtual - Designing with Multi-Gigabit Serial I/O
Learn how to employ serial transceivers in 7 series designs.The focus is on:Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, ...

Virtual - Designing with SystemVerilog
Provides a thorough introduction to SystemVerilog constructs for design.This focus is on:Writing RTL code using the new constructs available in SystemVerilogReviewing new data types, structs, unions, arrays, procedura...

Virtual - Designing with the Versal ACAP: Architecture and Methodology
This course helps you to learn about Versal™ ACAP architecture and design methodology. The emphasis of this course is on:▪ Reviewing the architecture of the Versal ACAP▪ Describing the different engines available in t...

Virtual - Designing with the Versal ACAP: Network on Chip
This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is us...

Virtual - Designing with the Versal ACAP: PCI Express Systems
This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement aVersal ACAP PCI Express® solution in custom applications to...

Virtual - Designing with the Versal ACAP: Power and Board Design
This course provides a system-level understanding of power and thermal issues related to designing with the Versal™ ACAP. The emphasis of this course is on: Estimating power using power analysis Managing thermal desig...

Virtual - Designing with the Zynq UltraScale+ RFSoC
Provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the RFSoC family in gen...

Virtual - Designing with Verilog
Provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and behavioral co...

Virtual - Designing with Versal AI Engine 1 - Architecture and Design Flow
This course describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using dataflow graphs), the data communications between the PL and AI ...

Virtual - Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
This course describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster d...