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Classroom - Designing with Ethernet MAC Controllers
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity.The course covers:Learning the basics of the Ethernet standard, protocol, and OSI modelPerforming simulation to understand fund...

Classroom - Designing with Multi-Gigabit Serial I/O (PLC2 version)
Designing with Multi-Gigabit Serial I/O (PLC2 version)

Classroom - Designing with RFSoC Converters (PLC2 version)
The new XILINX Zynq UltraScale+ RFSoC devices allow very fast data converter interfaces. This 2-day course starts with a description of the new RF­SoC family in general. You will enumerate the key elements of the RFSo...

Classroom - Designing with the Spartan-7 Family (PLC2 version)
Designing with the Spartan-7 Family (PLC2 version)

Classroom - Designing with the UltraScale and UltraScale+ Architectures
Introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking res...

Classroom - Designing with the Versal ACAP: PCI Express Systems
This course introduces the features andcapabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™architecture. Learn how to implement a Versal ACAP PCI Express® solution incustom applications to i...

Classroom - Designing with the Zynq UltraScale+ RFSoC
Provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the RFSoC family in gen...

Classroom - Designing with UltraScale FPGA Transceivers
Learn how to employ serial transceivers in UltraScale™ FPGA designs.The focus is on:Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock corr...

Classroom - Designing with Verilog
Provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and behavioral co...

Classroom - Designing with Versal AI Engine 1 - Architecture and Design Flow
This course describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using dataflow graphs), the data communications between the PL and AI ...