Xilinx-Prod-LMS Offerings


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Classroom - Designing with DFX Using the Vivado Design Suite
Learn how to construct, implement, and download aDynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite.This course covers both the tool flow and mechanics of successfully creating aDFX design. &nb...

Classroom - Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite
Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® DesignSuite. This course covers both the tool flow and mechanics of successfullycreating a DFX design. Th...

Classroom - Designing with Ethernet MAC Controllers
Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity.The course covers:Learning the basics of the Ethernet standard, protocol, and OSI modelPerforming simulation to understand fund...

Classroom - Designing with Multi-Gigabit Serial I/O
Learn how to employ serial transceivers in 7 series designs.The focus is on:Identifying and using the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, ...

Classroom - Designing with SystemVerilog
Provides a thorough introduction to SystemVerilog constructs for design.This focus is on:Writing RTL code using the new constructs available in SystemVerilogReviewing new data types, structs, unions, arrays, procedura...

Classroom - Designing with the UltraScale and UltraScale+ Architectures
Introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking res...

Classroom - Designing with the Versal ACAP: Architecture and Methodology
This course helps you to learn about Versal™ ACAP architecture and design methodology. The emphasis of this course is on:▪ Reviewing the architecture of the Versal ACAP▪ Describing the different engines available in t...

Classroom - Designing with the Versal ACAP: Network on Chip
This course introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is us...

Classroom - Designing with the Zynq UltraScale+ RFSoC
Provides an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family with a special emphasis on the Data Converter and Soft-Decision FEC blocks.The focus is on:Describing the RFSoC family in gen...

Classroom - Designing with Verilog
Provides a thorough introduction to the Verilog language.The emphasis is on:Writing efficient hardware designsPerforming high-level HDL simulationsEmploying structural, register transfer level (RTL), and behavioral co...