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C-based Design - High-Level Synthesis with the Vivado HLx Tool
This content provides a thorough introduction to the Vivado High-Level Synthesis (HLS) tool.The focus is on:Covering synthesis strategies and featuresImproving throughput, area, interface creation, latency, testbench ...
Designing FPGAs Using the Vivado Design Suite 1
This training content offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.The courses provide experience with:Creating a Vivado Design Su...
Designing FPGAs Using the Vivado Design Suite 2
This content builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.Learn how to build a more effective FPGA design.The focus is on:Using synchronous design techniquesUtilizing the Viva...
Designing FPGAs Using the Vivado Design Suite 3
This content builds further on the previous Designing FPGAs Using the Vivado Design Suite 1 & 2.Learn how to effectively employ timing closure techniques.The courses includes:Demonstrating timing closure technique...
Designing FPGAs Using the Vivado Design Suite 4
Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware.The focus is on:Applying timing constraints for source-synchronous and system-synchronous interfacesUtilizing floorplanning techniq...
Classroom - C-based design: High-Level Synthesis with the Vivado HLx Tool
Provides a thorough introduction to the Vivado High-Level Synthesis (HLS) tool.The focus is on:Covering synthesis strategies and featuresImproving throughput, area, interface creation, latency, testbench coding, and c...
Classroom - Designing FPGAs Using the Vivado Design Suite 2
Learn how to build a more effective FPGA design:The focus is on:Using synchronous design techniquesUtilizing the Vivado® IP integrator to create a sub-systemEmploying proper HDL coding techniques to improve design per...
Classroom - Designing FPGAs Using the Vivado Design Suite 3
Learn how to effectively employ timing closure techniques.This course includes:Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuitsShowing optimum HDL coding techniques ...
Classroom - Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users
This course will update experienced ISE® software users on how to utilize the Vivado® Design Suite.The emphasis is on:Reviewing the underlying database and static timing analysis (STA) mechanismsUtilizing Tcl for navi...
Virtual - C-based design: High-Level Synthesis with the Vivado HLx Tool
Provides a thorough introduction to the Vivado High-Level Synthesis (HLS) tool.The focus is on:Covering synthesis strategies and featuresImproving throughput, area, interface creation, latency, testbench coding, and c...