This content provides a system-level understanding of power and thermal issues related to designing with the Versal™ ACAP.Updated 1.2022 - v2021.2

This content helps you to learn about Versal® ACAP architecture and design methodology.Updated 1.2022 - v2021.2

This content introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is u...

This content introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications ...

This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and A...

This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...

This content covers the advanced features of the Versal® ACAP AI Engine, including debugging an application in the Vitis™ unified software platform, using filter intrinsics, implementing a system design in hardware, a...

With the Versal Adaptive Compute Acceleration Platform (ACAP) family XILINX introduces versions of these devices with a special feature, the AI Engine. The AI Engine offers high performance, low latency capabilities f...

With the new XILINX ACAP family (Adaptive Compute Acceleration Platform) hardware developers are enabled for the classic methods of HDL development, i.e. also by using HLS tool. And with Vitis a huge capability of met...

This 3-day course will enable the software developer to get the best possible start on software development for the Versal ACAP family. This first explains the Versal ACAP architecture and the unified Vitis Software D...