This course describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using dataflow graphs), the data communications between the PL and AI ...

This course describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster d...

This course covers the advanced features of the Versal™ ACAP AI Engine, including debugging an application in the Vitis™ unified software platform, using filter intrinsics, implementing a system design in hardware, an...

This course is a combination of two courses related to the Versal™ AI Engine which are often taken back to back. This combination offers students the savings of time and money by removing the redundancies between the ...

This course helps you to learn about Versal™ ACAP embedded processor architecture and design methodology.The emphasis of this course is on:Reviewing the architecture of the Versal ACAPDescribing the different engines ...

This 4-day course introduces engineers to developing verification environments using the Universal Verification Methodology (UVM) library. This class shows you how to create an UVM test bench structure for your DUT, w...

This course helps you to learn about Versal™ ACAP programmable logic architecture and design methodology.The emphasis of this course is on: Reviewing the architecture of the Versal ACAPUtilizing the hardened blocks av...

With the Versal Adaptive Acceleration Platform (ACAP) Xilinx introduces devices with a special AI Engine unit.The AI Engine offers high performance, low latency capabilities for advanced data processing.This course he...

With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family - Adaptive Compute Acceleration Platform. The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivit...