CURRICULUM BY DESIGN PROCESS
Courses
Designing with the UltraScale and UltraScale+ Architectures
This content introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional...
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Designing with VHDL
This comprehensive curriculum is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer ...
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Designing with Versal AI Engine 1 - Architecture and Design Flow
This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and A...
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Designing with the Versal ACAP: Network on Chip
This content introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is u...
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High-Level Synthesis with the Vitis HLS Tool
This content provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool.Updated 1.2022 - v2021.2
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Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...
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Designing with the Versal ACAP: Architecture and Methodology
This content helps you to learn about Versal® ACAP architecture and design methodology.Updated 1.2022 - v2021.2
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Designing FPGAs Using the Vivado Design Suite 1
This training content offers introductory training on the Vivado® Design Suite and demonstrates the FPGA design flow for those uninitiated to FPGA design.The courses provide experience with:Creating a Vivado Design Su...
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Designing FPGAs Using the Vivado Design Suite 2
This content builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.Learn how to build a more effective FPGA design.The focus is on:Using synchronous design techniquesUtilizing the Viva...
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UltraFast Design Methodology
Learn how to improve design speed and reliability by using the UltraFast Design Methodology and the Vivado® Design Suite.The focus is on:Optimizing system reset design and synchronization circuitsEmploying best practi...
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Designing FPGAs Using the Vivado Design Suite 3
Learn how to effectively employ timing closure techniques.This course includes:Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuitsShowing optimum HDL coding techniques ...
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Designing with Verilog
This comprehensive content is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. These courses address targeting Xilinx devices specif...
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Smoke_Test_Cert
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