In this curriculum path, you will learn how to identify component, performance, I/O, and data transfer requirements at a system level. For the Versal ACAP, this includes solution application mapping to the PS, PL, and AI Engine.
Courses
Designing with the UltraScale and UltraScale+ Architectures
This content introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.The emphasis is on:Introducing CLB resources, clock management resources (MMCM and PLL), global and regional...
Using Xilinx Alveo Cards to Accelerate Dynamic Workloads
Free OnDemand Course:Xilinx Alveo™ accelerator cards can help you achieve the highest performance, accelerate any workload, and deploy solutions in the cloud or on premises for data center workloads.The focus of this ...
This content is structured to provide designers with an overview of the hard block capabilities for the Zynq® UltraScale+™ RFSoC family. Special emphasis is placed on the Data Converter and Soft-Decision FEC blocks.Po...
This content provides system architects with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family. The emphasis is on Utilizing power management strategies effectively, Leveraging the pl...
Designing with Versal AI Engine 1 - Architecture and Design Flow
This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and A...
This content introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is u...
Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
This content describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster ...
Using Accelerated Applications with the Vision AI Starter Kit & System-on-Module (SOM)
Free OnDemand CourseThis content will help you learn about the Xilinx Kria System-on-Module (SOM) and Vision AI Starter Kit, enabling you to accelerate applications using the Vision AI Starter Kit right out of the box...
Designing with the Versal ACAP: PCI Express Systems
This content introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the Versal™ architecture. Learn how to implement a Versal ACAP PCI Express® solution in custom applications ...
Learn how to improve design speed and reliability by using the UltraFast Design Methodology and the Vivado® Design Suite.The focus is on:Optimizing system reset design and synchronization circuitsEmploying best practi...
Using Vison-based Applications with the Kria KV260 Vision AI Starter Kit and System-on-Module
This content will help you learn about the Xilinx Kria™ System-on-Module (SOM) and Kria KV260 Vision AI Starter Kit, enabling you to accelerate vision based applications using the KV260 Starter Kit right out of the bo...
Accelerating Applications with the Vitis Unified Software Environment
Learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis™ unified software environment targeting both data center (DC) and embedded applications.The emphasis of this course is o...
Developing Multimedia Solutions with the Video Codec Unit Using the GStreamer Framework
Learn how to build and run complex multimedia applications targeting Zynq® UltraScale+™ MPSoC EV devices with the help of the GStreamer framework. This course also illustrates how the use of the hardened video codec u...
