System Design Flow
Demonstrates the Vitis compiler flow to integrate a compiled AI Engine design graph (libadf.a) with additional kernels implemented in the PL region of the device (including HLS and RTL kernels) and link them for use on a target platform. You can call then these compiled hardware functions from a host program running in the Arm® processor in the Versal device or on an external x86 processor.
{Lecture, Lab}
Updated 1.2022 - v2021.2
1 . System Design Flow
2 . System Design Flow - Lab