Classroom - Compact VITIS (PLC2 version)
Sequential processing or data path speed is a bottleneck in many high-end systems based on CPUs. Whereas FPGAsprovide massive parallel data processing along with optimized data path. A system with CPU and FPGA combination would be an ideal solution by utilizing best of both worlds. But FPGA development is more complex and often hard to achieve time-to-market requirements. Xilinx developed a hard- and software-based ecosystem to utilizeFPGAs as a kind of remote processing element along with CPU. Xilinx’ new unified software environment, called VITIS,offers the capabilities to integrate CPU code within FPGA kernels which helps to accelerate FPGA based development by staying in high level programming languages and using OpenCL API for application offloading and data path acceleration. In this course, you will learn how to develop, debug, and profile new or existing C/C++ and RTL applications with VITIS targeting both data center (DC) and embedded applications.
Youwill also learn how to run designs on the XILINX ALVEO accelerator board.