Virtual - Designing FPGAs Using the Vivado Design Suite 4
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Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware.
The focus is on:
  • Applying timing constraints for source-synchronous and system-synchronous interfaces
  • Utilizing floorplanning techniques
  • Employing advanced implementation options
  • Utilizing Xilinx security features
  • Identifying advanced FPGA configurations
  • Debugging a design at the device startup phase
  • Using Tcl scripting in non-project batch flows
This is the final course in the Designing FPGAs Using the Vivado Design Suite series.
View the course description PDF for more details.

4/21/2021 - 4/22/2021
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 8
Venue : Online - Technically Speaking
Address :
7/29/2021 - 7/30/2021
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : Online – FasterTechnology LLC
Address :
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