Virtual - Introduction to Universal Verification Methodology (UVM) (Hardent version)
This 4-day course introduces engineers to developing verification environments using the Universal Verification Methodology (UVM) library. This class shows you how to create an UVM test bench structure for your DUT, which includes both stimulus generation and analysis.The class addresses how to create test cases that generate stimulus using sequences and System Verilog randomization constructs. The class teaches how to write analysis components such as scoreboards and coverage collectors, and howto create, integrate, and use a register model of your DUT. A good portion of class time will be spent applying principles learned in lecture to hands-on labs.