Virtual - Designing FPGAs Using the Vivado Design Suite 2
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Learn how to build a more effective FPGA design:
The focus is on:
  • Using synchronous design techniques
  • Utilizing the Vivado® IP integrator to create a sub-system
  • Employing proper HDL coding techniques to improve design performance
  • Debugging a design with multiple clock domains
This course build on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
View the course description PDF for more details.

7/8/2021 - 7/9/2021
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 15
Venue : Online – FasterTechnology LLC
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