Virtual - Designing FPGAs Using the Vivado Design Suite 2
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Learn how to build a more effective FPGA design:
The focus is on:
  • Using synchronous design techniques
  • Utilizing the Vivado® IP integrator to create a sub-system
  • Employing proper HDL coding techniques to improve design performance
  • Debugging a design with multiple clock domains
This course build on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
View the course description PDF for more details.

11/9/2020 - 11/10/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : Online – FasterTechnology LLC
Address :
12/7/2020 - 12/9/2020
Time Zone : (GMT+03:00) Moscow, St. Petersburg, Volgograd
Seats Remaining : 5
Venue : RUS, Moscow - MIREA
Address : 78, prospect Vernadskogo,Moscow,RUSSIA