Virtual - Designing FPGAs Using the Vivado Design Suite 2
Learn how to build a more effective FPGA design:
The focus is on:
  • Using synchronous design techniques
  • Utilizing the Vivado® IP integrator to create a sub-system
  • Employing proper HDL coding techniques to improve design performance
  • Debugging a design with multiple clock domains
This course build on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
View the course description PDF for more details.

10/10/2021 - 10/31/2021
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 13
Venue : ISR, Petah-Tikva - Logtel Headquarters
Address : 32 Shacham St, Ramat-Siv Industrial Park,Petah-Tikva,ISRAEL
11/16/2021 - 11/18/2021
Time Zone : (GMT-05:00) Eastern Time (US & Canada)
Seats Remaining : 20
Venue : Online - BLT - $299 per day
Address : www.bltinc.com
2/10/2022 - 2/11/2022
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : USA, Houston - Faster Technology Online
Address :