Classroom - Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment
Rating
Learn how to develop, debug, and profile new or existing OpenCL™, C/C++, and RTL applications in the SDAccel™ development environment for use on Xilinx FPGAs.
The focus is on learning how to utilize techniques in the SDAccel environment to:
  • Reduce latency
  • Utilize the massive parallelism inherent to FPGAs
  • Optimize throughput
  • Pipeline for performance
This course also provides an introduction to targeting the Alveo™ accelerator card.
View the course description PDF for more details.

4/6/2020 - 4/7/2020
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Frankfurt - TBD PLC2 Venue
Address : TBD,Frankfurt,GERMANY
4/13/2020 - 4/14/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA
5/13/2020 - 5/14/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
7/1/2020 - 7/2/2020
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Stuttgart - TBD PLC2 Venue
Address : TBD,Stuttgart,GERMANY
9/16/2020 - 9/17/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
11/25/2020 - 11/26/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA