Classroom - Designing with VHDL
Rating
Provides a thorough introduction to the VHDL language.
The emphasis is on:
  • Writing efficient hardware designs
  • Performing high-level HDL simulations
  • Employing structural, register transfer level (RTL), and behavioral coding styles
  • Targeting Xilinx devices specifically and FPGA devices in general
  • Utilizing best coding practices
View the course description PDF for more details.

10/5/2020 - 10/7/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
10/5/2020 - 10/7/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA
12/1/2020 - 12/3/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 3
Venue : To Be Determined
Address :
12/14/2020 - 12/16/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
3/1/2021 - 3/2/2021
Time Zone : (GMT+01:00) Brussels, Copenhagen, Madrid, Paris
Seats Remaining : 12
Venue : ESP, Madrid - Universidad Autonoma de Madrid
Address : Fco Tomas y Valiente 11,School of Engineering,Madrid,SPAIN