Classroom - Designing with Verilog
Provides a thorough introduction to the Verilog language.
The emphasis is on:
  • Writing efficient hardware designs
  • Performing high-level HDL simulations
  • Employing structural, register transfer level (RTL), and behavioral coding styles
  • Targeting Xilinx devices specifically and FPGA devices in general
  • Utilizing best coding practices
This course covers Verilog 1995 and 2001.
View the course description PDF for more details.

7/4/2022 - 7/6/2022
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA
7/18/2022 - 7/20/2022
Time Zone : (GMT+08:00) Kuala Lumpur, Singapore
Seats Remaining : 8
Venue : Techsource Systems - Singapore
Address : 10 Ubi Crescent #06-48 Ubi Techpark Lobby C,Singapore,SINGAPORE