Classroom - Designing with Verilog
Rating
Provides a thorough introduction to the Verilog language.
The emphasis is on:
  • Writing efficient hardware designs
  • Performing high-level HDL simulations
  • Employing structural, register transfer level (RTL), and behavioral coding styles
  • Targeting Xilinx devices specifically and FPGA devices in general
  • Utilizing best coding practices
This course covers Verilog 1995 and 2001.
View the course description PDF for more details.

10/5/2020 - 10/5/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
11/2/2020 - 11/4/2020
Time Zone : (GMT+09:00) Yakutsk
Seats Remaining : 9
Venue : To Be Determined
Address :
12/14/2020 - 12/14/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA