Classroom - Verification with SystemVerilog
Rating
Provides an introduction to SystemVerilog constructs for verification.
This course covers:
  • Writing testbenches to verify a design under test (DUT) utilizing the constructs available in SystemVerilog
  • Reviewing object-oriented modeling, data types, reusable tasks and functions, randomization, code coverage, assertions, and the Direct Programming Interface (DPI)
View the course description PDF for more details.

10/8/2020 - 10/9/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
12/17/2020 - 12/18/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA