Classroom - Designing with SystemVerilog
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Provides a thorough introduction to SystemVerilog constructs for design.
This focus is on:
  • Writing RTL code using the new constructs available in SystemVerilog
  • Reviewing new data types, structs, unions, arrays, procedural blocks, re-usable tasks, functions, and packages
  • Targeting and optimizing Xilinx devices using SystemVerilog
View the course description PDF for more details.

8/4/2020 - 8/6/2020
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
10/6/2020 - 10/7/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
12/16/2020 - 12/18/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
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