Classroom - Designing FPGAs Using the Vivado Design Suite 4
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Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware.
The focus is on:
  • Applying timing constraints for source-synchronous and system-synchronous interfaces
  • Utilizing floorplanning techniques
  • Employing advanced implementation options
  • Utilizing Xilinx security features
  • Identifying advanced FPGA configurations
  • Debugging a design at the device startup phase
  • Using Tcl scripting in non-project batch flows
This is the final course in the Designing FPGAs Using the Vivado Design Suite series.
View the course description PDF for more details.

9/2/2020 - 9/2/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
11/5/2020 - 11/5/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
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