Classroom - Designing FPGAs Using the Vivado Design Suite 3
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Learn how to effectively employ timing closure techniques.
This course includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design
This course builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.
View the course description PDF for more details.

8/31/2020 - 9/1/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
11/3/2020 - 11/4/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 10
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
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