Classroom - Designing FPGAs Using the Vivado Design Suite 2
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Learn how to build a more effective FPGA design:
The focus is on:
  • Using synchronous design techniques
  • Utilizing the Vivado® IP integrator to create a sub-system
  • Employing proper HDL coding techniques to improve design performance
  • Debugging a design with multiple clock domains
This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
View the course description PDF for more details.

7/6/2021 - 7/8/2021
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7/7/2021 - 7/8/2021
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
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Address : Cereslaan 10b,Heesch,THE NETHERLANDS
7/12/2021 - 7/13/2021
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7/21/2021 - 7/23/2021
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8/4/2021 - 8/6/2021
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8/11/2021 - 8/13/2021
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8/16/2021 - 8/17/2021
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Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA
8/17/2021 - 8/19/2021
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9/5/2021 - 9/13/2021
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9/14/2021 - 9/16/2021
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10/12/2021 - 10/14/2021
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11/2/2021 - 11/4/2021
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11/30/2021 - 12/2/2021
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12/22/2021 - 12/30/2021
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