Classroom - Designing FPGAs Using the Vivado Design Suite 2

Overview
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Learn how to build a more effective FPGA design:

The focus is on:

Using synchronous design techniques
Utilizing the Vivado® IP integrator to create a sub-system
Employing proper HDL coding techniques to improve design performance
Debugging a design with multiple clock domains

This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

View the course description PDF for more details.

10/6/2021 - 10/7/2021
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 6
Venue : NLD - Heesch - CoreVision Headquarters
Address : Cereslaan 10b,Heesch,THE NETHERLANDS

10/11/2021 - 10/12/2021
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

10/12/2021 - 10/14/2021
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : To Be Determined
Address :

11/2/2021 - 11/4/2021
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : To Be Determined
Address :

11/8/2021 - 11/9/2021
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

11/30/2021 - 12/2/2021
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : To Be Determined
Address :

12/22/2021 - 12/30/2021
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 20
Venue : To Be Determined
Address :

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