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Overview
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Learn how to build a more effective FPGA design:

The focus is on:

Using synchronous design techniques
Utilizing the Vivado® IP integrator to create a sub-system
Employing proper HDL coding techniques to improve design performance
Debugging a design with multiple clock domains

This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

View the course description PDF for more details.

11/4/2019 - 10/30/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 7
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA

4/6/2020 - 4/7/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

4/9/2020 - 4/10/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 13
Venue : USA, MN, Orono - MAPS Venue
Address : 2500 Shadywood Rd,Suite 505,Orono,MN,USA

5/6/2020 - 5/7/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : USA, IL, Naperville - MAPS Venue
Address : Naperville, IL,Morgan Advanced Programmable Systems, Inc.,Naperville,IL,USA

5/11/2020 - 5/12/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

7/9/2020 - 7/10/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : USA, MO, St. Louis - MAPS Venue 2
Address : St. Louis,Morgan Advanced Programmable Systems, Inc.,St. Louis,MO,USA

7/13/2020 - 7/14/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : USA, MO, St. Louis - MAPS Venue 2
Address : St. Louis,Morgan Advanced Programmable Systems, Inc.,St. Louis,MO,USA

7/16/2020 - 7/17/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 14
Venue : USA, IL, Schaumburg - MAPS Venue 1
Address : Schaumburg, IL,Morgan Advanced Programmable Systems, Inc.,Schaumburg,IL,USA

Questions?