Classroom - Designing FPGAs Using the Vivado Design Suite 2
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Learn how to build a more effective FPGA design:
The focus is on:
  • Using synchronous design techniques
  • Utilizing the Vivado® IP integrator to create a sub-system
  • Employing proper HDL coding techniques to improve design performance
  • Debugging a design with multiple clock domains
This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.
View the course description PDF for more details.

11/4/2019 - 10/30/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 7
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA
11/9/2020 - 11/10/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : To Be Determined
Address :
12/7/2020 - 12/8/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 3
Venue : To Be Determined
Address :