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Overview
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Learn how to build a more effective FPGA design:

The focus is on:

Using synchronous design techniques
Utilizing the Vivado® IP integrator to create a sub-system
Employing proper HDL coding techniques to improve design performance
Debugging a design with multiple clock domains

This course builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

View the course description PDF for more details.

11/4/2019 - 10/30/2020
Time Zone : (GMT+00:00) GMT
Seats Remaining : 7
Venue : AUT, Vienna - So-Logic Office
Address : Lustkandlg. 52,Vienna,AUSTRIA

8/12/2020 - 8/14/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : IDEC
Address : N26, KAIST, 291 Daehak-ro Yuseong-gu,Daejeon,NORTH KOREA

8/17/2020 - 8/18/2020
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

8/18/2020 - 8/20/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 10
Venue : KOR, Seoul - Libertron Headquarters
Address : #1111, Dangsan SK V1 Center, 11, Dangsan-ro 41-gil, Yeongdeungpo-gu,Seoul,SOUTH KOREA

8/20/2020 - 8/21/2020
Time Zone : (GMT+08:00) Taipei
Seats Remaining : 16
Venue : TWN, Taipei - E-Elemements Office
Address : 5F, No.61, Lane76, Ruiguang Rd.,Taipei,TAIWAN

9/7/2020 - 9/8/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

10/12/2020 - 10/13/2020
Time Zone : (GMT+09:00) Seoul
Seats Remaining : 9
Venue : KOR, Seoul - Wedu Office
Address : #B820, Tera tower 2, 201 Songpa-daero, Songpa-gu,Seoul,SOUTH KOREA

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