This course will update experienced ISE® software users on how to utilize the Vivado® Design Suite.
The emphasis is on:
- Reviewing the underlying database and static timing analysis (STA) mechanisms
- Utilizing Tcl for navigating the design, creating Xilinx design constraints (XDC), and creating timing reports
- Applying appropriate timing constraints for SDR, DDR, source-synchronous, and system-synchronous interfaces
- Creating path-specific, false path, and min/max timing constraints as well as learning about timing constraint priority in the Vivado timing engine
- Utilizing a project-based scripting flow
- Employing FPGA design best practices and the UltraFast Design Methodology to improve design speed and reliability