Classroom - Designing with the UltraScale and UltraScale+ Architectures
Introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.
The emphasis is on:
  • Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
  • Describing improvements to the dedicated transceivers and Transceiver Wizard
  • Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
  • Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® Design Suite
View the course description PDF for more details.

11/17/2021 - 11/18/2021
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Stuttgart - TBD PLC2 Venue
Address : TBD,Stuttgart,GERMANY
12/19/2021 - 12/26/2021
Time Zone : (GMT-08:00) Pacific Time (US & Canada)
Seats Remaining : 20
Venue : To Be Determined
Address :