Classroom - Designing with the UltraScale and UltraScale+ Architectures
Introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.
The emphasis is on:
  • Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
  • Describing improvements to the dedicated transceivers and Transceiver Wizard
  • Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
  • Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® Design Suite
View the course description PDF for more details.

6/11/2020 - 6/12/2020
Time Zone : (GMT-06:00) Central Time (US & Canada)
Seats Remaining : 16
Venue : USA, TX, Richardson - Avnet Office
Address : 3101 E. Pres George Bush,Richardson,TX,USA