Classroom - Designing with the 7 Series Families
Rating
Learn how to effectively utilize and properly design for the primary architectural resources found in 7 series devices.
The focus is on:
  • Utilizing 7 series CLB, clocking, memory, DSP, and I/O resources
  • Describing the dedicated hardware resources available (PCI Express® technology, analog-to-digital converters, and gigabit transceivers)
  • Employing proper HDL coding techniques to get the most out of device resources
This course supports both experienced and less experienced FPGA designers who have already completed the Designing FPGAs Using the Vivado Design Suite 1 course.
View the course description PDF for more details.

9/11/2019 - 9/12/2019
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Berlin - TBD PLC2 Venue
Address : TBD,Berlin,GERMANY
11/28/2019 - 11/29/2019
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Stuttgart - TBD PLC2 Venue
Address : TBD,Stuttgart,GERMANY