Classroom - Zynq UltraScale+ MPSoC for the Hardware Designer
This course provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.
The emphasis is on:
  • Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • Reviewing the various power domains and their control structure
  • Illustrating the processing system (PS) and programmable logic (PL) connectivity
  • Utilizing QEMU to emulate hardware behavior
View the course description PDF for more details.

12/8/2021 - 12/9/2021
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 6
Venue : NLD - Heesch - CoreVision Headquarters
Address : Cereslaan 10b,Heesch,THE NETHERLANDS