Classroom - Signal Integrity and Board Design for Xilinx FPGAs
Learn when and how to apply signal integrity techniques to high-speed interfaces between Xilinx FPGAs and other components.
This course combines design techniques and methodology with relevant background concepts of high-speed bus and clock design, including transmission line termination, loading, and jitter.
You will work with IBIS models and complete simulations using Mentor Graphics Hyper Lynx. Other topics include managing PCB effects and on-chip termination.
View the course description PDF for more details.