Classroom - Advanced Versal AI Engine (PLC2 version)
With the Versal Adaptive Compute Acceleration Platform (ACAP) family XILINX introduces versions of these devices with a special feature, the AI Engine. The AI Engine offers high performance, low latency capabilities for advanced data processing. This course enables algorithm programmers to deploy C/ C++ kernels on Versal AI Engine. First, the basic elements of the Versal AI Engine are described with regards to the internal VLIW processing units, interfaces and connections to data path and memory hierarchy in the regular grid of the AIE tiles are presented. With the Vitis tools the AI Engine is set up to run acceleration functions written in C/C++ code. This shows how to implement a discrete AI Engine kernel including debugging capabilities and analysis features of the Vitis Toolchain along examples and labs. For signal processing setups a tool flow is presented that uses dataflow graphs to connect multiple kernels and shows the capabilities of the Versal AI Engine array. Deploying these dataflow graphs the course moves onto the system level design flow with AI Engine based kernels in Vitis. An important aspect of system design with Versal devices is application partitioning between the different heterogeneous compute engines that are available. To create heterogeneous system design, the data flow graph may route multiple compute domains as PL and AI Engine. The common features to interface these graph elements effectively, such as streams, are explained and can be experienced in hands on lab exercises.

9/5/2022 - 9/7/2022
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Freiburg - PLC2 Office
Address : Hugstmattweg 30,Freiburg,GERMANY
12/19/2022 - 12/21/2022
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Munchen - TBD PLC2 Venue
Address : TBD,Munchen,GERMANY