Classroom - Advanced ZYNQ UltraScale+MPSoC for HW Designers (PLC2 Version)
This three-days course provides both the tool- and architecture- specific aspects necessary for development with the XILINX ZYNQ UltraScale+ MPSoC device.
The focus in this course is on embedded hardware development with the XILINXVIVADO tool using the IP-Integrator, including software development using the Vitis tool. The overall architecture of the ZYNQ UltraScale+ MPSoC Processing System (PS) is discussed in detail to understand the architecture in the silicon Processing System which interfaces to the Programmable Logic (PL). The APU includes the ARM Cortex-A53 cores, the RPU includes the Cortex-R5 cores and the PMU includes a Micro Blaze system. And it will be necessary to protect and isolate accesses in a system of shared peripherals and memory if MPSoC based designs are running simultaneously.
For this connection of AXI-based IPs in the Programmable Logic (PL) to the Processing System (PS), it is essential to understand the AXI protocol with features like coherency management and virtual system management. The final section of this course includes Platform Management, Power Management and Inter-Processor-Interrupt concepts.

9/28/2022 - 9/30/2022
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Frankfurt - TBD PLC2 Venue
Address : TBD,Frankfurt,GERMANY
12/19/2022 - 12/21/2022
Time Zone : (GMT+01:00) Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna
Seats Remaining : 12
Venue : DEU, Stuttgart - TBD PLC2 Venue
Address : TBD,Stuttgart,GERMANY