Classroom - Designing with Versal AI Engine 1 - Architecture and Design Flow
This course describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using dataflow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features.

The emphasis of this course is on:
  • Illustrating the AI Engine architecture
  • Designing single AI Engine kernels using the Vitis™ unified software platform
  • Designing multiple AI kernels using data flow graphs with the Vitis IDE
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
  • Analyzing and debugging kernel performance