Introduction to UVM (Hardent)
Course Details
Length: 18 Hours
Number of Labs: 11
Number of Chapter: 1
Current Version:
Number of Demos: 0

Overview

This on-demand course introduces engineers to UVM (Universal Verification Methodology), the exciting open-source library that has quickly become the reference verification methodology for the electronic design community.
The course teaches you the key base classes in the library and how to use them. You will learn about the structure of a UVM testbench, the core components required for a working testbench, and how to use TLM communication between the components of your testbench. You will see how to create transactor classes like drivers and monitors and analysis components like scoreboards and coverage collectors. You will learn the best strategies for connecting your UVM testbench to the RTL DUT. Other library features you will learn to deploy are factory creation and overrides, environment customization using configuration objects, scalable stimulus generation with sequences, and how to design your testbench for reuse.
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