Designing with Verilog
Course Details
Length: 26 Hours
Number of Labs: 9
Number of Chapter: 36
Current Version: 2021.1
Number of Demos: 1

Overview

This comprehensive content is a thorough introduction to the Verilog language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. These courses address targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This training content combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn advanced coding techniques that will increase your overall Verilog proficiency and enhance your FPGA optimization. This content covers Verilog 1995 and 2001.

Updated 10.2021
  • USD Price = 299
Training Credit Price = 3 TC
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