Designing FPGAs Using the Vivado Design Suite 4
Course Details
Length: 21 Hours
Number of Labs: 11
Number of Chapter: 29
Current Version: 2021.1
Number of Demos: 0

Overview

Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware.
The focus is on:
  • Applying timing constraints for source-synchronous and system-synchronous interfaces
  • Utilizing floorplanning techniques
  • Employing advanced implementation options
  • Utilizing Xilinx security features
  • Identifying advanced FPGA configurations
  • Debugging a design at the device startup phase
  • Using Tcl scripting in non-project batch flows
This is the final course in the Designing FPGAs Using the Vivado Design Suite series.
Updated 9.2021
  • USD Price = 199
Training Credit Price = 2 TC
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