Designing FPGAs Using the Vivado Design Suite 3
Course Details
Length: 20 Hours
Number of Labs: 12
Number of Chapter: 21
Current Version: 2021.1
Number of Demos: 4

Overview

Learn how to effectively employ timing closure techniques.
This course includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design
This content builds further on the previous Designing FPGAs Using the Vivado Design Suite courses
Updated 9.2021
  • USD Price = 199
Training Credit Price = 2 TC
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