Designing FPGAs Using the Vivado Design Suite 2

Course Details

Length: 25 Hours

Number of Labs: 10

Number of Chapter: 23

Current Version: 2021.2

Number of Demos: 0

Overview

This content builds on the concepts from the Designing FPGAs Using the Vivado Design Suite 1 course.

Learn how to build a more effective FPGA design.

The focus is on:

Using synchronous design techniques
Utilizing the Vivado® IP integrator to create a sub-system
Employing proper HDL coding techniques to improve design performance
Debugging a design with multiple clock domains

Updated 1.2022 - v2021.2

CHAPTERS

UltraFast Design Methodology - Design Creation

Synchronous Design Techniques

Resets

Register Duplication

UltraScale Architecture Clocking Resources

Versal ACAP - Clocking Architecture Introduction

UltraScale Architecture I/O Resources (FPGAs Suite 2)

Versal ACAP: SelectIO Resources

Clocking and I/O Resources in the Versal ACAP

Creating and Packaging Custom IP

Using an IP Container

Designing with the IP Integrator

Timing Constraints Editor

Report Clock Networks

Timing Summary Report

Clock Group Constraints

Introduction to Timing Exceptions

Power Analysis and Optimization Using the Vivado Design Suite

Configuration Process

HDL Instantiation Debug Probing Flow

Scripting in Vivado Design Suite Project Mode

Design Analysis Using Tcl Commands

Designing FPGAs Using the Vivado Design Suite 2 Full Course Quiz

OTHER FORMATS

On Demand Trainings

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USD Price = 199

Training Credit Price = 2 TC

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