SLVR - Designing FPGAs Using the Vivado Design Suite 3
Course Details
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Number of Chapter: 20
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Overview

This content builds further on the previous Designing FPGAs Using the Vivado Design Suite 1 & 2.
Learn how to effectively employ timing closure techniques.
The courses includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design
Updated 9.2020
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