Designing with the Versal ACAP: Network on Chip
Course Details
Length: 8 Hours
Number of Labs: 2
Number of Chapter: 9
Current Version: 2021.2
Number of Demos: 0

Overview

This content introduces the Versal™ ACAP network on chip (NoC) to users familiar with Xilinx devices. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC is used to efficiently move data within the device.
The emphasis of this course is on:
  • Enumerating the major components comprising the NoC architecture in the Versal ACAP
  • Implementing a basic design using the NoC
  • Configuring the NoC for efficient data movement
Updated 1.2022 - v2021.2
  • USD Price = 99
Training Credit Price = 1 TC
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