Designing with Versal AI Engine 1 - Architecture and Design Flow
  • USD Price = 199
Training Credit Price = 2 TC


This content describes the Versal™ AI Engine architecture, how to program the AI Engines (single kernel programming and multiple kernel programming using data flow graphs), the data communications between the PL and AI Engines, and how to analyze the kernel program using various debugger features.

The emphasis of these courses are on:
  • Illustrating the AI Engine architecture
  • Designing single AI Engine kernels using the Vitis™ unified software platform
  • Designing multiple AI kernels using data flow graphs with the Vitis IDE
  • Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
  • Analyzing and debugging kernel performance
Updated 8.2021
What,s New: 
  • Deprecated support for PL kernels in the AI Engine graph 
  • System Generator for DSP is now part of Vitis Model Composer