Designing with the Versal ACAP: Architecture and Methodology

Course Details

Length:

Number of Labs:

Number of Chapter: 26

Current Version:

Number of Demos:

Overview

In this content you will learn about Versal™ ACAP architecture and design methodology.

The emphasis of this course is on:

Reviewing the architecture of the Versal ACAP
Describing the different engines available in the Versal architecture and what resources they contain
Utilizing the hardened blocks available in the Versal architecture
Using the design tools and methodology provided by Xilinx to create complex systems
Describing the network on chip (NoC) and AI Engine concepts and ther architectures
Performing system-level simulation and debugging

CHAPTERS

Versal ACAP: Introduction

Versal ACAP: Architecture Overview

Versal ACAP: Design Tool Flow

Versal ACAP: Adaptable Engines (PL)

Versal ACAP: Processing System

Versal ACAP: PMC and Boot and Configuration

Versal ACAP: SelectIO Resources

Versal ACAP - Clocking Architecture

Versal ACAP: System Interrupts

Versal ACAP: Timers, Counters, and RTC

Versal ACAP: Software Build Flow

Versal ACAP: Software Stack

Versal ACAP: DSP Engine

Versal ACAP: AI Engine

Versal ACAP: NoC Introduction and Concepts

Versal ACAP: Device Memory

Versal ACAP: Programming Interfaces

Versal ACAP: Application Partitioning

Versal ACAP: PCI Express & CCIX

Versal ACAP: Serial Transceivers

Versal ACAP: Power and Thermal Solutions

Versal ACAP: Debugging

Versal ACAP: Security Features

Versal ACAP: System Simulation

Versal ACAP: System Design Methodology

Designing with the Versal ACAP: Architecture and Methodology Full Course Quiz

OTHER FORMATS

On Demand Trainings

Virtual Classroom

Live Classroom

USD Price = 299

Training Credit Price = 3 TC

Show Detailed Course Description

Questions?

Related Courses

No data to display