Designing FPGAs Using the Vivado Design Suite 4

Course Details

Length: 21 Hours

Number of Labs: 11

Number of Chapter: 27

Current Version: 2021.1

Number of Demos: 0

Overview

Learn how to use the advanced aspects of the Vivado® Design Suite and Xilinx hardware.

The focus is on:

Applying timing constraints for source-synchronous and system-synchronous interfaces
Utilizing floorplanning techniques
Employing advanced implementation options
Utilizing Xilinx security features
Identifying advanced FPGA configurations
Debugging a design at the device startup phase
Using Tcl scripting in non-project batch flows

This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

CHAPTERS

UltraFast Design Methodology - Design Closure

Scripting in Vivado Design Suite Non-Project Mode

Hierarchical Design

Managing IP in Remote Locations

I/O Timing Scenarios

System-Synchronous I/O Timing

Source-Synchronous I/O Timing

Timing Constraints Priority

Introduction to Floorplanning

Design Analysis and Floorplanning

Congestion

Introduction to the Vivado Store

Incremental Compile Flow

Timing Closure Using Physical Optimization Techniques

Vivado Design Suite ECO Flow

Power Management Techniques

Daisy Chains and Gangs in Configuration

Bitstream Security

Vivado Design Suite Debug Methodology

Trigger and Debug at Device Startup

Trigger Using the Trigger State Machine in the Vivado Logic Analyzer

Debugging the Design Using Tcl Commands

Using Procedures in Tcl Scripting

Using Lists in Tcl Scripting

Using Regular Expressions in Tcl Scripting

Debugging and Error Handling in Tcl Scripts

Designing FPGAs Using the Vivado Design Suite 4 Full Course Quiz

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USD Price = 199

Training Credit Price = 2 TC

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