Zynq UltraScale+ MPSoC for the Hardware Designer
Course Details
Length: 22 Hours
Number of Labs: 6
Number of Chapter: 12
Current Version: 2021.2
Number of Demos: 2


This content provides hardware designers with an overview of the capabilities and support for the Zynq® UltraScale+™ MPSoC family from a hardware architectural perspective.
The emphasis is on:
  • Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
  • Reviewing the various power domains and their control structure
  • Illustrating the processing system (PS) and programmable logic (PL) connectivity
  • Utilizing QEMU to emulate hardware behavior
Updated 3.2022 - v2021.2
  • USD Price = 199
Training Credit Price = 2 TC
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