Designing FPGAs Using the Vivado Design Suite 3
  • USD Price = 200
Training Credit Price = 2 TC
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Overview

Learn how to effectively employ timing closure techniques.
This course includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design
This curriculum builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.
View the course description PDF for more details.
What's new for 2019.2:
  • Timing Simulation: Additional information on retiming
  • Report QoR: Use of machine learning to predict top three implementation strategies
Courses

UltraFast Design Methodology - Implem...

Vivado Design Suite Non-Project Mode

Baselining

Pipelining

Inference

Revision Control Systems in the Vivad...

Timing Simulation

Synchronization Circuits

Report Clock Interaction

Report Datasheet

Report QoR

Dynamic Power Estimation Using Vivado...

Configuration Modes

Netlist Insertion Debug Probing Flow

Sampling and Capturing Data in Multip...

JTAG to AXI Master Core

Debug Flow in an IP Integrator Block ...

Remote Debugging Using the Vivado Log...

Manipulating Design Properties Using Tcl

Designing FPGAs Using the Vivado Desi...

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