Designing FPGAs Using the Vivado Design Suite 3
  • USD Price = 200
Training Credit Price = 2 TC


Learn how to effectively employ timing closure techniques.
This content includes:
  • Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
  • Showing optimum HDL coding techniques that help with design timing closure
  • Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design 
This curriculum builds further on the previous Designing FPGAs Using the Vivado Design Suite courses.

View the course description PDF for more details. 
What's new for 2019.2: 
  • Timing Simulation:Additional information on retiming 
  • Report QoR: Use of machine learning to predict top three implementation strategies