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Designing FPGAs Using the Vivado Design Suite 3
Designing FPGAs Using the Vivado Design Suite 3
Course Details
Length:
20 Hours
Number of Labs:
12
Number of Chapter:
20
Current Version:
2021.1
Number of Demos:
4
Overview
This content builds further on the previous Designing FPGAs Using the Vivado Design Suite 1 & 2.
Learn how to effectively employ timing closure techniques.
The courses includes:
Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits
Showing optimum HDL coding techniques that help with design timing closure
Illustrating the advanced capabilities of the Vivado® logic analyzer to debug a design
Updated 9.2020
CHAPTERS
UltraFast Design Methodology - Implementation
Vivado Design Suite Non-Project Mode
Baselining
Pipelining
Inference
Revision Control Systems in the Vivado Design Suite
Timing Simulation
Synchronization Circuits
Report Clock Interaction
Report Datasheet
Report QoR
Dynamic Power Estimation Using Vivado Power Report
Configuration Modes
Netlist Insertion Debug Probing Flow
Sampling and Capturing Data in Multiple Clock Domains
JTAG to AXI Master Core
Debug Flow in an IP Integrator Block Design
Remote Debugging Using the Vivado Logic Analyzer
Manipulating Design Properties Using Tcl
Designing FPGAs Using the Vivado Design Suite 3 Full Course Quiz
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USD Price = 199
Training Credit Price = 2 TC
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