Designing with the UltraScale and UltraScale+ Architectures
Course Details
Length: 26 Hours
Number of Labs: 13
Number of Chapter: 16
Current Version: 2021.1
Number of Demos: 2

Overview

This content introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers.
The emphasis is on:
  • Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
  • Describing improvements to the dedicated transceivers and Transceiver Wizard
  • Reviewing the Memory Interface Generator (MIG) and DDR4 memory interface capabilities
  • Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado® Design Suite
Updated 8.2021
  • USD Price = 199
Training Credit Price = 2 TC
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Kintex UltraScale FPGA KCU105 Evaluation Kit
KCU105
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